1. Field of the Invention
Embodiments of the invention relate to static random access memory (SRAM) to be used for storage on integrated circuit devices, and more particularly to advanced SRAM cells using one or more fin field-effect transistor (FinFET) structures. The present invention also relates to the design layout and manufacturing process for fabricating SRAM cells with such fin field-effect transistor structures.
2. Description of the Prior Art
Modern digital data processors generally use several different types of memory devices to answer different performance and functional requirements. Dynamic memories generally store data as charge in a capacitor to allow much faster access, and can be selectively addressed for storing smaller amounts of data each time. However, dynamic memories must be periodically refreshed to compensate for charge that may leak from its capacitors, leading to undesirable longer access time.
Static memory devices, such as static random access memories (SRAMs) with many rows and columns (e.g., arrays) of SRAM storage cells are widely used on integrated circuit devices. Each storage cell includes a bistable circuit, which does not require refreshing. Each bistable circuit comprises at least two transistors and additional selection/pass transistors, and can be switched from one bistable state to another bistable state at a faster speed. The switching speed of each bistable circuit is determined by the resistance and capacitance of the control electrodes of the transistors and the connection of the transistors within the circuit, thereby determining the slew rate of its output voltage. In addition to the desirability of forming larger numbers of SRAM memory cells and arrays on a chip of reasonable size, there is substantial incentive toward size reduction and integrated density increase in each cell. As a result, the resistance and capacitance of transistors and their connections in the SRAM cells can be minimized to improve device performance.
Because conventional SRAMs tend to occupy 50% or more chip area and limit the amount of other logic devices on the chip, recent advances in FinFET transistor technology have made advanced SRAM cells with improved FinFET transistor structures to minimize footprint/bit-cell area, thereby occupying much smaller chip area. In contrast to the prior planar MOS transistors with channels formed at a semiconductor substrate surface, FinFET transistors have three-dimensional (3D) channel region.
FIG. 1 is a schematic view of one example of a FinFET transistor structure 10, which comprises a substrate 18, a source 11, a drain 12, a gate insulator layer 13 and a gate conductor layer 14. In the FinFET transistor structure 10, the channel for the transistor is formed on the sides and the top of a raised “fin”-like structure (e.g., a fin 16), which comprises at least one or more semiconductor materials. The gate conductor layer 14, typically a metal gate, extends over the fin 16 and a gate insulator layer 13, is disposed between the gate conductor layer 14 and the fin 16. At least three surfaces are utilized to provide more current paths in a channel region (not shown) being covered by the gate insulator layer 13 and the gate conductor layer 14 and between the source 11 and the drain 12. Thus, the FinFET transistor structure 10 has better current driving capability than conventional planar FET transistors. As compared to planar transistors, the three-dimensional (3D) shape of the channel region of FinFET transistors in a SRAM cell allows for an increased gate width and a reduced gate length without increased silicon area, provides a reasonable channel width characteristic at a low silicon area cost, and enables the reduction of the overall scale of the SRAM devices. With the use of currently known masking techniques that provide good manufacturing yield, aggressive semiconductor process scaling can be obtained for a minimum feature size of 15 nm and smaller.
In general, a design layout of a SRAM array includes “bit cells” disposed between a pair of imaginary bit lines (BL) with bit line metal contacts arranged thereon in columns. In a design layout, imaginary rows of word lines are also used to separate bit cells. In addition, “bit cells” are formed into arrays in dense area and surrounded by “dummy edge cells” in isolation area or current connection area. The dummy edge cells are generally used to generate a timing signal, to perform a reinforcing function, to replace failed cells and/or to help improve process uniformity, such as etching uniformity concerns during device fabrication. Each bit cell can have, for example, a total of 6 FinFET transistors (6T) connected to single port, or eight FinFET transistors (8T) connected to dual port.
SRAM memory cells and arrays are fabricated by forming metal contacts such as word line contacts, bit line contacts, VSS contacts and VCC contacts, etc., over FinFET transistors to electrically connect these SRAM memory cells and arrays together and ensure normal read and write operations. Word line contacts are electrically connected by higher interconnect layer(s) such as first metal (M1) layer; bit line contacts are electrically connected by higher interconnect layer(s) such as M1, first via (V1) layer and second metal layer (M2).
In applying prior design layout rules, however, problems arose during the fabrication of high-density small-sized SRAM FinFET cell arrays. It was found that, when a current is applied, most of the fabricated metal contacts connected to the source and drain regions of the FinFET transistors near the boundary of a dummy edge cell have resulted in undesirable electrical short to their neighboring dummy gates at or near the edge of the dummy edge cells.
The reason for such electrical short is that, due to pattern density effect, after patterning, the sizes of those metal contact holes at or near a dummy edge cell are larger than the sizes of other metal contact holes within the dense area of a bit cell. What's more adverse is that optical proximity correction (OPC) will even enlarge the sizes of these metal contact holes because they are near isolation area. As a result, the dummy gate of a dummy edge cell becomes too close to the metal contacts and the electrical current goes short through the dummy gate. Such kind of undesirable electrical short is extremely damaging to the formed circuit devices.
During regular SRAM operations, a regular electrical path is going from a high VCC supply voltage (e.g., applying from PMOS to a metal contact) to a ground or VSS voltage (e.g., via NMOS to another metal contact nearby). When the undesirable electrical short happens, the electrical path will now go through the dummy gate of a dummy edge cell closest to the bit line metal contacts, instead of going through the regular electrical path, and the memory devices will fail to perform.
Therefore, there is still a need for an improved design layout of small size FinFET memory device and a method of preparing such an improved device layout and fabricating such improved devices to avoid undesirable electrical short between a high VDD supply voltage of a metal contact to a low VSS voltage of another metal contact nearby through the dummy gate.